Digital IP Engineer

Job Description

Appealing points: 

• Opportunity to work across the full IP/SOC development lifecycle including architecture, RTL design, verification, synthesis, P&R, and STA, enhancing advanced VLSI engineering skills
• Lead high-quality digital IP development using UVM/OVM, SystemVerilog Assertions, constrained random testing, and Cadence EDA flows in a cutting-edge engineering environment
• Take on a leadership role in Tokyo by driving cross-site program execution, strengthening both technical expertise and project management capabilities

Annual Salary:  8 Million Yen and above

Responsibilities

• Participate actively in various phases of the IP/SOC design process, including architecture, RTL design, verification, synthesis, place and route (P&R), and static timing analysis (STA).
• Utilize advanced verification methodologies such as UVM/OVM to ensure high quality design outputs.
• Develop and execute constrained random testing and debugging strategies to identify and resolve issues effectively.
• Write and maintain scripts in Perl or Python to automate processes and enhance productivity.
• Define coverage space and develop coverage models to ensure comprehensive testing.
• Implement SystemVerilog Assertions (SVA) to enhance verification processes.
• Oversee the execution of the IP Factory Model, ensuring alignment with project goals.
• Utilize Cadence EDA flows for design and verification tasks, ensuring adherence to industry standards.
• Conduct static timing analysis, parasitic extraction, place and route, IR drop analysis, and DRC checks using industry standard CAD tools.
• Lead and coordinate program execution across various sites, fostering collaboration and communication among team members.

Job Qualification: 

• 10+ years of experience in Digital IP Engineering with a degree in Electronics or Electrical Engineering.
• Proficient in digital communication protocols such as UART / SPI / I2C / etc.
• Strong expertise in VLSI UVM methodology.
• Solid verification skills, including problem solving, constrained random testing, and debugging.
• Experience with Cadence EDA flows at an advanced level.
• Excellent oral and written communication skills.
• Bachelor's or Master's degree in Electronics or Electrical Engineering.
• 10 15 years of relevant experience in Digital IP Engineering.
• Proven track record of successful project execution and team leadership.
• If you are a motivated and experienced Digital IP Engineer looking to take on a leadership role, we encourage you to apply and join our dynamic team in Tokyo

Preferred Skills

• Experience in defining coverage space and writing coverage models.
• Familiarity with System Verilog Assertions.
• Leadership Skill.

Language & Cultural Fluency

• Native Japanese with strong facilitation and business writing capability.
• Fluent English for global collaboration and delivery artifacts.

Company

This company is a leading foreign-affiliated solutions and services provider in the information, communications, and technology (ICT) industry. With more than 130,000 employees in 90 countries, they provide innovative IT solutions to nearly 1000 global customers, including Fortune 500 companies.

【Measures against passive smoking】

No smoking indoors allowed